MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 460
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Advance Information
460
CWP[5:0] — Command Word Pointer Field
A trigger pending state is required because both queues cannot be
active at the same time. The status of queue 2 is changed to trigger
pending when a trigger event occurs for queue 2 while queue 1 is
active. In the opposite case, when a trigger event occurs for queue 1
while queue 2 is active, queue 2 is aborted and the status is reported
as queue 1 active, queue 2 suspended. So due to the priority scheme,
only queue 2 can be in the trigger pending state.
Two transition cases cause the queue 2 status to be trigger pending
before queue 2 is shown to be in the active state. When queue 1 is
active and there is a trigger pending on queue 2, after queue 1
completes or pauses, queue 2 continues to be in the trigger pending
state for a few clock cycles. The fleeting status conditions are:
Figure 19-12
QADC goes through the transition from queue 1 active to queue 2
active.
The queue status field is affected by QADC stop mode. Because all
of the analog logic and control registers are reset, the queue status
field is reset to queue 1 idle, queue 2 idle.
During debug mode, the queue status field is not modified. The queue
status field retains the status it held prior to freezing. As a result, the
queue status can show queue 1 active, queue 2 idle, even though
neither queue is being executed during freeze.
The command word pointer (CWP) denotes which CCW is executing
at present or was last completed. CWP is a read-only field with a valid
range of 0 to 63; write operations have no effect.
When a queue enters the paused state, CWP points to the CCW with
the pause bit set. While in pause, the CWP value is maintained until
a trigger event occurs on either queue. Usually, the CWP is updated
a few clock cycles before the queue status field shows that the queue
has become active. For example, a read of CWP may point to a CCW
in queue 2, while the queue status field shows queue 1 paused and
queue 2 trigger pending.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
• Queue 1 idle with queue 2 trigger pending
• Queue 1 paused with queue 2 trigger pending
Go to: www.freescale.com
displays the status conditions of the QS field as the
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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