MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 598

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
22.14.7.1 Breakpoint Address Comparators
22.14.7.2 Memory Breakpoint Counters
22.14.8 OnCE Trace Logic
Advance Information
598
The breakpoint address comparators are not externally accessible. Each
compares the memory address stored in MAL with the contents of BABx,
as masked by BAMx, and signals the control logic when a match occurs.
The 16-bit Memory Breakpoint Counter Registers (MBCA and MBCB)
are loaded with a value equal to the number of times, minus one, that a
memory access event should occur before a memory breakpoint is
declared. The memory access event is specified by the RCx4–RCx0 and
BCx4–BCx0 bits in the OCR and by the Memory Base and Mask
Registers. On each occurrence of the memory access event, the
breakpoint counter, if currently non-zero, is decremented. When the
counter has reached the value of zero and a new occurrence takes
place, the ISBKPTx signal is asserted and causes the CPU’s BRKRQ
input to be asserted. The MBCx can be read or written through the OnCE
serial interface.
Anytime the breakpoint registers are changed, or a different breakpoint
event is selected in the OCR, the breakpoint counter must be written
afterward. This assures that the OnCE breakpoint logic is reset and that
no previous events will affect the new breakpoint event selected.
The OnCE trace logic allows the user to execute instructions in single or
multiple steps before the device returns to debug mode and awaits
OnCE commands from the debug serial port. The OnCE trace logic is
independent of the M•CORE trace facility, which is controlled through
the trace mode bits in the M•CORE Processor Status Register. The
OnCE trace logic block diagram is shown in
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Figure
22-13.
MOTOROLA