MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 463

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.8.7 Conversion Command Word Table (CCW)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
CWPQ2[5:0] — Queue 2 Command Word Pointer Field
The conversion command word (CCW) table is 64 half-word (128 byte)
long RAM with 10 bits of each entry implemented. The CCW table is
written by the user and is not modified by the QADC. Each CCW
requests the conversion of one analog channel to a digital result. The
CCW specifies the analog channel number, the input sample time, and
whether the queue is to pause after the current CCW.
Finally, when queue 1 operation is terminated after a CCW is read
that is pointed to by BQ2, CWP points to BQ2 while CWPQ1 points to
the last queue 1 CCW.
During stop mode, CWPQ1 is reset to 63, because the control
registers and the analog logic are reset. When debug mode is
entered, CWPQ1 is not changed; it points to the last executed CCW
in queue 1.
CWPQ2[5:0] points to the last queue 2 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect.
CWPQ2 always points to the last executed CCW in queue 2,
regardless which queue is active.
In contrast to CWP, CPWQ2 is updated when a conversion result is
written. When the QADC finishes a conversion in queue 2, both the
result register is written and CWPQ2 is updated.
During stop mode, CWPQ2 is reset to 63 because the control
registers and the analog logic are reset. When debug mode is
entered, CWPQ2 is not changed; it points to the last executed CCW
in queue 2.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
Advance Information
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