MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 230
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Second Generation FLASH for M•CORE (SGFM)
10.8 SGFM User Mode
10.8.1 Read Operations
10.8.2 Write Operations
Advance Information
230
Normal operation of the SGFM occurs in user mode. The SGFM
registers, subject to the restrictions previously noted, can generally be
read and written. Reads of the SGFM array generally occur normally and
writes behave according to the setting of the KEYACC bit in SGFMCR.
Program, erase, and verify operations are initiated by the CPU. Special
cases of user mode apply when the CPU is in low power or debug modes
and when the MCU boots in master mode or emulation mode.
A valid read operation occurs whenever a transfer request is initiated by
the M•CORE, the MLB address is equal to an address within the valid
range of the SGFM memory space, and the read/write control indicates
a read cycle. Aligned read accesses (byte, halfword, or word) complete
in one system clock cycle. Misaligned accesses are not allowed and
result in a cycle termination transfer error.
In order to reduce power at low system clock frequencies, the sense
amplifier timeout (SATO) block minimizes the time during which the
sense amplifiers are enabled for read operations. The sense amplifier
enable signals to the FLASH timeout after approximately 50 ns.
A valid write operation occurs whenever a transfer request is initiated by
the M•CORE, the MLB address is equal to an address within the valid
range of the SGFM memory space, and the read/write control indicates
a write cycle.
The action taken on a valid SGFM array write depends on the
subsequent user command issued as part of a valid command
sequence. Only aligned 32-bit write operations are allowed to the SGFM
array. Byte and halfword write operations will result in a cycle termination
transfer error.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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