MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 403
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
SPE — SPI System Enable Bit
SWOM — SPI Wired-OR Mode Bit
MSTR — Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
The SPE bit enables the SPI and dedicates SPI port pins [3:0] to SPI
functions. When SPE is clear, the SPI system is initialized but in a
low-power disabled state. Reset clears SPE.
The SWOM bit configures the output buffers of SPI port pins [3:0] as
open-drain outputs. SWOM controls SPI port pins [3:0] whether they
are SPI outputs or general-purpose outputs. Reset clears SWOM.
The MSTR bit selects SPI master mode or SPI slave mode operation.
Reset clears MSTR.
The CPOL bit selects an inverted or non-inverted SPI clock. To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears CPOL.
The CPHA bit delays the first edge of the SCK clock. Reset sets
CPHA.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SPI enabled
0 = SPI disabled
1 = Output buffers of SPI port pins [3:0] open-drain
0 = Output buffers of SPI port pins [3:0] CMOS drive
1 = Master mode
0 = Slave mode
1 = Active-low clock; SCK idles high
0 = Active-high clock; SCK idles low
1 = First SCK edge at start of transmission
0 = First SCK edge 1/2 cycle after start of transmission
Serial Peripheral Interface Module (SPI)
Go to: www.freescale.com
Serial Peripheral Interface Module (SPI)
Memory Map and Registers
Advance Information
403
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