MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 462

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
19.8.6.2 QADC Status Register 1 (QASR1)
Advance Information
462
Address: 0x00ca_0012 and 0x00ca_0013
Reset:
Reset:
Read:
Read:
Write:
Write:
Stop mode resets this register ($3f3f).
Read: Anytime
Write: Never
CWPQ1[5:0] — Queue 1 Command Word Pointer Field
Finally, when queue 1 operation is terminated after a CCW is read
that is pointed to by BQ2, the CWP points to the same CCW as BQ2.
During stop mode, CWP is reset to 0 because the control registers
and the analog logic are reset. When debug mode is entered, CWP is
not changed; it points to the last executed CCW.
CWPQ1[5:0] points to the last queue 1 CCW executed. This is a
read-only field with a valid range of 0 to 63; writes have no effect.
CWPQ1 always points to the last executed CCW in queue 1,
regardless of which queue is active.
In contrast to CWP, CPWQ1 is updated when a conversion result is
written. When the QADC finishes a conversion in queue 1, both the
result register is written and CWPQ1 is updated.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Bit 15
Bit 7
0
0
0
0
Figure 19-13. QADC Status Register 1 (QASR1)
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= Writes have no effect and the access terminates without a transfer error exception.
14
0
0
6
0
0
CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10
CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20
13
1
5
1
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
1
4
1
11
1
3
1
10
1
2
1
9
1
1
1
MOTOROLA
Bit 8
Bit 0
1
1