MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 604
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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JTAG Test Access Port and OnCE
Advance Information
604
Reset:
Reset:
Read:
Read:
Write:
Write:
Reserved bits represent the internal processor state. Restore these bits
to their original value after a debug session is completed, for example,
when a OnCE command is issued with the GO and EX bits set and not
ignored. Set these bits to 1s while instructions are executed during a
debug session.
FFY — Feed Forward Y Operand Bit
FDB — Force Debug Enable Mode Bit
SZ1 and SZ0 — Prefetch Size Field
This control bit is used to force the content of the WBBR to be used
as the Y operand value of the first instruction to be executed following
an update of the CPUSCR. This gives the debug firmware the
capability of updating processor registers by initializing the WBBR
with the desired value, setting the FFY bit, and executing a MOV
instruction to the desired register.
Setting this control bit places the processor in debug enable mode. In
debug enable mode, execution of the BKPT instruction as well as
recognition of the BRKRQ input causes the processor to enter debug
mode, as if the DBGRQ input had been asserted.
This control field is used to drive the CPU SIZ1 and SIZ0 outputs on
the first instruction pre-fetch caused by issuing a OnCE command
with the GO bit set and not ignored. It should be set to indicate a 16-bit
size, for example, 0b10. This field should be restored to its original
value after a debug session is completed, for example, when a OnCE
command is issued with the GO and EX bits set and not ignored.
Freescale Semiconductor, Inc.
For More Information On This Product,
RSVD
Bit 15
Bit 7
FDB
0
JTAG Test Access Port and OnCE
Figure 22-15. Control State Register (CTL)
Go to: www.freescale.com
RSVD
SZ1
14
6
0
RSVD
SZ0
13
5
0
RSVD
TC2
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
4
0
RSVD
TC1
11
3
0
RSVD
TC0
10
2
0
RSVD
RSVD
9
1
MOTOROLA
RSVD
Bit 8
FFY
Bit 0
0
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