MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 585
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.14.3 OnCE Interface Signals
22.14.3.1 Internal Debug Request Input (IDR)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Figure 22-8
The following paragraphs describe the OnCE interface signals to other
internal blocks associated with the OnCE controller. These signals are
not available externally, and descriptions are provided to improve
understanding of OnCE operation.
The internal debug request input is a hardware signal which is used in
some implementations to force an immediate debug request to the CPU.
If present and enabled, it functions in an identical manner to the control
function provided by the DR control bit in the OCR. This input is
maskable by a control bit in the OCR.
Freescale Semiconductor, Inc.
ISTRACE
ISBKPT
For More Information On This Product,
ISDR
Figure 22-7. OnCE Controller and Serial Interface
JTAG Test Access Port and OnCE
REGISTER
READ
Go to: www.freescale.com
shows the interface signals for the OnCE controller.
CONTROL/
DECODER
STATUS
OnCE
CPU
REGISTER
WRITE
OnCE COMMAND REGISTER
JTAG Test Access Port and OnCE
AND CONTROL
OnCE STATUS
CONTROLLER
REGISTERS
OnCE TAP
Functional Description
Advance Information
TDI
TCLK
TMS
TDO
585
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