MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 35

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Figure
17-10 SCI Pullup and Reduced Drive Register (SCIPURD) . . . . . . . 371
17-11 SCI Port Data Register (SCIPORT) . . . . . . . . . . . . . . . . . . . . 372
17-12 SCI Data Direction Register (SCIDDR) . . . . . . . . . . . . . . . . . 373
17-13 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
17-14 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
17-15 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 381
17-16 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
17-17 Start Bit Search Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 384
17-18 Start Bit Search Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 385
17-19 Start Bit Search Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . 385
17-20 Start Bit Search Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . 386
17-21 Start Bit Search Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . 386
17-22 Start Bit Search Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . . 387
17-23 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
17-24 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
17-25 Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . . . . 392
17-26 Loop Operation (LOOPS = 1, RSRC = 0). . . . . . . . . . . . . . . . 393
18-1 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
18-2 SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . . . 402
18-3 SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . . . 405
18-4 SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . . . 406
18-5 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . . . . 408
18-6 SPI Data Register (SPIDR). . . . . . . . . . . . . . . . . . . . . . . . . . . 409
18-7 SPI Pullup and Reduced Drive Register (SPIPURD) . . . . . . . 410
18-8 SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . . . . 411
18-9 SPI Port Data Direction Register (SPIDDR) . . . . . . . . . . . . . .412
18-10 Full-Duplex Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
18-11 SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . .417
18-12 SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . .418
18-13 Transmission Error Due to Master/Slave Clock Skew . . . . . . 419
19-1 QADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
19-2 QADC Input and Output Signals. . . . . . . . . . . . . . . . . . . . . . .432
19-3 QADC Module Configuration Register (QADCMCR) . . . . . . . 437
19-4 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . . . . 438
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