MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 426

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
Advance Information
426
19.8.5
19.8.5.1
19.8.5.2
19.8.5.3
19.8.6
19.8.6.1
19.8.6.2
19.8.7
19.8.8
19.8.8.1
19.8.8.2
19.8.8.3
19.9
19.9.1
19.9.2
19.9.2.1
19.9.2.2
19.9.3
19.9.3.1
19.9.3.2
19.9.3.3
19.9.3.4
19.9.3.5
19.9.3.6
19.9.3.7
19.9.3.8
19.9.3.9
19.10 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
19.10.1 Queue Priority Timing Examples . . . . . . . . . . . . . . . . . . . . 478
19.10.1.1
19.10.1.2
19.10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
19.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
19.10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
19.10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
19.10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
19.10.6.1
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
Conversion Command Word Table (CCW) . . . . . . . . . . . . 463
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468
Result Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . 442
QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . 445
QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . 448
QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . 453
QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . 462
Right-Justified Unsigned Result Register (RJURR) . . . . 468
Left-Justified Signed Result Register (LJSRR) . . . . . . . 469
Left-Justified Unsigned Result Register (LJURR) . . . . . 470
External Multiplexing Operation . . . . . . . . . . . . . . . . . . .471
Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . . 473
Analog-to-Digital Converter Operation . . . . . . . . . . . . . .474
Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . 475
Channel Decode and Multiplexer . . . . . . . . . . . . . . . . . . 476
Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476
Digital-to-Analog Converter (DAC) Array . . . . . . . . . . . . 476
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
Successive Approximation Register. . . . . . . . . . . . . . . . 477
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477
Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . . 481
Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . . 495
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