MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 482
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Queued Analog-to-Digital Converter (QADC)
Advance Information
482
The situation diagrams also show when key status bits are set.
Table 19-13
Below the queue execution flows are three sets of blocks that show the
status information that is made available to the user. The first two rows
of status blocks show the condition of each queue as:
The third row of status blocks shows the 4-bit QS status register field that
encodes the condition of the two queues. Two transition status cases,
QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in
and S3) show what happens when a new trigger event is recognized
before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1
each queue while that queue is still working on the previously recognized
trigger event. The trigger overrun error status bit is set, and the
premature trigger event is otherwise ignored. A trigger event that occurs
before the servicing of the previous trigger event is through does not
disturb the queue execution in progress.
Trigger overrun
•
•
•
•
•
Freescale Semiconductor, Inc.
error (TOR)
For More Information On This Product,
CF flag
PF flag
Queued Analog-to-Digital Converter (QADC)
Idle
Active
Pause
Suspended (queue 2 only)
Trigger pending
Bit
Go to: www.freescale.com
describes the status bits.
(Figure
Set when the end of the queue is reached
Set when a queue completes execution up through a pause bit
Set when a new trigger event occurs before the queue is finished
servicing the previous trigger event
Table 19-13. Status Bits
19-23), one trigger event is being recognized on
Figure 19-23
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Function
through
Figure 19-25
MOTOROLA
(S1, S2,
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