MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 530
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface Module (EBI)
20.3.1 Data Bus (D[31:0])
20.3.2 Show Cycle Strobe (SHS)
20.3.3 Transfer Acknowledge (TA)
20.3.4 Transfer Error Acknowledge (TEA)
20.3.5 Emulation Mode Chip Selects (CSE[1:0])
Advance Information
530
The three-state bidirectional data bus (D[31:0]) signals are the
general-purpose data path between the microcontroller unit (MCU) and
all other devices.
In master and emulation modes, show cycle strobe (SHS) is the strobe
for capturing address, controls, and data during show cycles. In master
mode this default functionality can be overridden to make the pin
function as digital I/O. See
and
mode, the SHS pin is configured as digital I/O (PE7) by default.
The transfer acknowledge (TA) signal indicates that the external data
transfer is complete. During a read cycle, when the processor
recognizes TA, it latches the data and then terminates the bus cycle.
During a write cycle, when the processor recognizes TA, the bus cycle
is terminated. TA is an input in master and emulation modes. In
single-chip mode, the TA pin is configured as digital I/O (PE6) by default.
The transfer error acknowledge (TEA) indicates an error condition exists
for the bus transfer. The bus cycle is terminated and the CPU begins
execution of the access error exception. TEA is an input in master and
emulation modes. In single-chip mode the TEA pin is configured a digital
I/O (PE5) by default.
The emulation mode chip select (CSE[1:0]) output signals provide
information for development support. In single-chip mode and master
mode, these pins are configured as digital I/O (PE4 and PE3) by default.
Freescale Semiconductor, Inc.
Table 12-3. Ports A–I Supported Pin
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
12.4.2.6 Port E Pin Assignment Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Functions. In single-chip
MOTOROLA
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