MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 508
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Advance Information
508
When any of the end-of-queue conditions is recognized, a queue
completion flag is set, and if enabled, an interrupt is requested. These
situations prematurely terminate queue execution:
•
•
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Queue 1 is higher in priority than queue 2. When a trigger event
occurs on queue 1 during queue 2 execution, the execution of
queue 2 is suspended by aborting the execution of the CCW in
progress, and queue 1 execution begins. When queue 1 execution
is complete, queue 2 conversions restart with the first CCW entry
in queue 2 or the first CCW of the queue 2 subqueue being
executed when queue 2 was suspended. Alternately, conversions
can restart with the aborted queue 2 CCW entry. The RESUME bit
in QACR2 selects where queue 2 begins after suspension. By
choosing to re-execute all of the suspended queue 2 CCWs
(RESUME = 0), all of the samples are guaranteed to have been
taken during the same scan pass. However, a high trigger event
rate for queue 1 can prevent completion of queue 2. If this occurs,
execution of queue 2 can begin with the aborted CCW entry
(RESUME = 1).
Any conversion in progress for a queue is aborted when that
queue’s operating mode is changed to disabled. Putting a queue
into the disabled mode does not power down the converter.
Changing a queue’s operating mode to another valid mode aborts
any conversion in progress. The queue restarts at its beginning
once an appropriate trigger event occurs.
For low-power operation, the stop bit can be set to prepare the
module for a loss of clocks. The QADC aborts any conversion in
progress when stop mode is entered.
When the QADC debug bit is set and the CPU enters background
debug mode, the QADC freezes at the end of the conversion in
progress. After leaving debug mode, the QADC resumes queue
execution beginning with the next CCW entry. Refer to
Debug Mode
Go to: www.freescale.com
for more information.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
19.5.1
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