MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 148

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset Controller Module
5.7.1.1 Power-On Reset
5.7.1.2 External Reset
5.7.1.3 Watchdog Timer Reset
5.7.1.4 Loss of Clock Reset
Advance Information
148
At power up, the reset controller asserts RSTOUT. RSTOUT continues
to be asserted until V
if PLL clock mode is selected, until the PLL achieves phase lock. Then
after approximately another 512 cycles, RSTOUT is negated and the
part begins operation.
Asserting the external RESET pin for at least four rising CLKOUT edges
causes the external reset request to be recognized and latched. The bus
monitor is enabled and the current bus cycle is completed. The reset
controller asserts RSTOUT for approximately 512 cycles after the
RESET pin is negated and the PLL has acquired lock. The part then exits
reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the
external RESET pin in stop mode causes an external reset to be
recognized.
A watchdog timer timeout causes timer reset request to be recognized
and latched. The bus monitor is enabled and the current bus cycle is
completed. If the RESET pin is negated and the PLL has acquired lock,
the reset controller asserts RSTOUT for approximately 512 cycles. Then
the part exits reset and begins operation.
This reset condition occurs in PLL clock mode when the LOCRE bit in
the SYNCR register is set and either the PLL reference or the PLL fails.
The reset controller asserts RSTOUT for approximately 512 cycles after
the PLL has acquired lock. The part then exits reset and begins
operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Reset Controller Module
DD
has reached a minimum acceptable level and,
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA