MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 168

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M•CORE M210 Central Processor Unit (CPU)
Advance Information
168
Arithmetic and logical operations are executed in a single cycle.
Multiplication is implemented with a 2-bit per clock, overlapped-scan,
modified Booth algorithm with early-out capability, to reduce execution
time for operations with small multipliers. Divide is implemented with a
1-bit per clock early-in algorithm. The find-first-one unit operates in one
clock cycle.
The program counter unit incorporates a dedicated branch address
adder to minimize delays during change of flow operations. Branch
target addresses are calculated in parallel with branch instruction
decode. Taken branches and jumps require only two clocks; branches
which are not taken execute in one clock cycle.
Memory load and store operations are provided for 8-bit (byte), 16-bit
(halfword), and 32-bit (word) data, with automatic zero extension for byte
and half-word load operations. These instructions can execute in as few
as two clock cycles. Load and store multiple register instructions allow
low overhead context save and restore operations. These instructions
can execute in (N+1) clock cycles, where N is the number of registers to
transfer.
A condition code/carry (C) bit is provided for condition testing or for use
in implementing arithmetic and logical operations with operands/results
greater than 32 bits. The C bit is typically set by explicit test/comparison
operations, not as a side-effect of normal instruction operation.
Exceptions to this rule occur for specialized operations where it is
desirable to combine condition setting with actual computation.
The processor uses autovectors for both normal and fast interrupt
requests. Fast interrupts take precedence over normal interrupts. Both
types have dedicated exception shadow registers. For service requests
of either kind, an automatic vector is generated when the request is
made.
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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