MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 540
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface Module (EBI)
20.8 Bus Exception Operation
20.8.1 Transfer Error Termination
20.8.2 Transfer Abort Termination
20.9 Emulation Support
20.9.1 Emulation Chip-Selects (CSE[1:0])
Advance Information
540
Normal bus cycle termination requires the assertion of the TA pin or the
internal transfer acknowledge signal. Minimal bus exception support is
provided by transfer error cycle termination. For transfer error cycle
termination, the external TEA pin or the internal transfer error
acknowledge signal is asserted. Transfer error cycle termination takes
precedence over normal cycle termination, provided TEA assertion
meets its timing constraints.
The internal bus monitor will assert the internal transfer error
acknowledge signal when TA response time is too long, based upon the
BMT[1:0] settings in the Chip Configuration Registers (CCR). See
4.7.3.1 Chip Configuration
External bus cycles which are aborted by the M•CORE, still have the
address, R/W, TC[2:0], TSIZ[1:0], CS (if used), OE (reads only), and
SHS (if used) driven to the external pins.
While in emulation mode or master mode, special emulator chip-selects
(CSE[1:0]) are driven externally to allow internal/external accesses to be
tracked by external hardware See
In emulation mode, all port registers are mapped externally.
CSE[1:0] = 10 whenever any emulated port registers are addressed.
The lower bits of the address bus indicate the register accessed within
the block.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
Register.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Table
20-4.
MOTOROLA
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