MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 477

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.9.3.6 Comparator
19.9.3.7 Bias
19.9.3.8 Successive Approximation Register
19.9.3.9 State Machine
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The DAC array provides a mechanism for the successive approximation
A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to
the least significant bit (LSB). The switching sequence is controlled by
the comparator and SAR logic. The sample capacitor samples and holds
the voltage to be converted.
During the approximation process, the comparator senses whether the
digitally selected arrangement of the DAC array produces a voltage level
higher or lower than the sampled input. The comparator output feeds
into the SAR which accumulates the A/D conversion result sequentially,
beginning with the MSB.
The bias circuit is controlled by the STOP signal to power-up and
power-down all the analog circuits.
The input of the SAR is connected to the comparator output. The SAR
sequentially receives the conversion value one bit at a time, starting with
the MSB. After accumulating the 10 bits of the conversion result, the
SAR data is transferred to the appropriate result location, where it may
be read by user software.
The state machine generates all timing to perform an A/D conversion. An
internal start-conversion signal indicates to the A/D converter that the
desired channel has been sent to the MUX. IST[1:0] denotes the desired
sample time. BYP determines whether to bypass the sample amplifier.
Once the end of conversion has been reached a signal is sent to the
queue control logic indicating that a result is available for storage in the
result RAM.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Functional Description
Advance Information
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