R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 26

• Manufacturer Part Number: R5F61668MZN50FPV
• Description: MCU FLASH 1024K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668MZN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.6
20.7
20.8
20.9
20.10 Usage Notes ...................................................................................................................... 990
Section 21 I
21.1
21.2
21.3
21.4
Rev. 1.00 Jan. 29, 2010 Page xxvi of xxxii
Processing of USB Standard Commands and Class/Vendor Commands ......................... 982
20.6.1
Stall Operations ................................................................................................................ 983
20.7.1
20.7.2
20.7.3
DMA Transfer .................................................................................................................. 986
20.8.1
20.8.2
20.8.3
Example of USB External Circuitry ................................................................................. 988
20.10.1 Receiving Setup Data........................................................................................ 990
20.10.2 Clearing the FIFO ............................................................................................. 990
20.10.3 Overreading and Overwriting the Data Registers ............................................. 990
20.10.4 Assigning Interrupt Sources to EP0.................................................................. 991
20.10.5 Clearing the FIFO When DMA Transfer is Enabled ........................................ 991
20.10.6 Notes on TR Interrupt ....................................................................................... 991
20.10.7 Restrictions on Peripheral Module Clock (Pφ) Operating Frequency............... 992
20.10.8 Notes on Deep Software Standby Mode when USB is Used............................ 992
Features............................................................................................................................. 993
Input/Output Pins.............................................................................................................. 995
Register Descriptions........................................................................................................ 996
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.3.6
21.3.7
21.3.8
21.3.9
Operation ........................................................................................................................ 1010
21.4.1
21.4.2
21.4.3
21.4.4
21.4.5
2
C Bus Interface 2 (IIC2)................................................................ 993
Processing of Commands Transmitted by Control Transfer............................. 982
Overview .......................................................................................................... 983
Forcible Stall by Application ............................................................................ 983
Automatic Stall by USB Function Module ....................................................... 985
Overview .......................................................................................................... 986
DMA Transfer for Endpoint 1 .......................................................................... 986
DMA Transfer for Endpoint 2 .......................................................................... 987
I
I
I
I
I
Slave Address Register (SAR)........................................................................ 1008
I
I
I
I
Master Transmit Operation............................................................................. 1011
Master Receive Operation .............................................................................. 1013
Slave Transmit Operation ............................................................................... 1015
Slave Receive Operation................................................................................. 1018
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ............................................................... 997
C Bus Control Register B (ICCRB) ............................................................... 999
C Bus Mode Register (ICMR)...................................................................... 1001
C Bus Interrupt Enable Register (ICIER)..................................................... 1002
C Bus Status Register (ICSR)....................................................................... 1005
C Bus Transmit Data Register (ICDRT) ...................................................... 1009
C Bus Receive Data Register (ICDRR)........................................................ 1009
C Bus Shift Register (ICDRS)...................................................................... 1009
C Bus Format................................................................................................ 1010