UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 143

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.2.8 Port 12
Remark Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
using port mode register 12 (PM12).
resistor option register 12 (PU12).
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input
for main system clock, external clock input for subsystem clock, external reset input, and clock input and data I/O for
flash memory programmer/on-chip debugger.
switch control register (MUXSEL).
clear RSTM to 0 when using P125/RESET as an external reset input.
P121/X1/TOOLC0
P122/X2/EXCLK/
TOOLD0
P125/RESET
P120 functions as an I/O port with an output latch. P120 can be set to the input mode or output mode in 1-bit units
P121 to P125 function as an Input port.
When used as an input port for P120 and P125, use of an on-chip pull-up resistor can be specified by pull-up
This port can also be used as pins for external interrupt request input, potential input for external low-voltage
The data output of the serial interface can be assigned to P120 of the 78K0/KC2-L by setting the port alternate
Set bit 5 (RSTM) of the reset pin mode register (RSTMASK) to 1 when using P125/RESET as an input port, and
Reset signal generation sets port 12 to input mode.
Figures 4-27 to 4-29 show block diagrams of port 12.
Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2)
Remark
( PD78F055x)
78K0/KY2-L
16 Pins
For how to connect a flash memory programmer using TOOLC0/X1, TOOLD0/X2, refer to CHAPTER 25
FLASH MEMORY. For how to connect TOOLC0/X1, TOOLD0/X2 and an on-chip debug emulator, refer
to CHAPTER 26 ON-CHIP DEBUG FUNCTION.
2. RESET/P125 is set in an external reset input after a reset release.
3. When using P120 for external low-voltage detection potential input, connect P120 to V
or subsystem clock (XT1, XT2), or to input an external clock for the main system clock
(EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or
external clock input mode must be set by using the clock operation mode select register
(OSCCTL) (for details, refer to 5.3 (1) Clock operation mode select register (OSCCTL) and (3)
Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of
the P121 to P124 pins are Input port pins).
resistor.
P121/X1/TOOLC0
P122/X2/EXCLK/
TOOLD0
P125/RESET
( PD78F056x)
78K0/KA2-L
20 Pins
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 4 PORT FUNCTIONS
P120/EXLVI/INTP0
P121/X1/TOOLC0
P122/X2/EXCLK/
TOOLD0
P125/RESET
( PD78F057x)
78K0/KB2-L
30 Pins
P120/EXLVI/INTP0
(/SO11)
P121/X1/TOOLC0
P122/X2/EXCLK/
TOOLD0
P123/XT1
P124/XT2/EXCLKS
P125/RESET
44 Pins
( PD78F058x)
78K0/KC2-L
P120/EXLVI/INTP0
(/SO11)
P121/X1/TOOLC0
P122/X2/EXCLK/
TOOLD0
P123/XT1
P124/XT2/EXCLKS
P125/RESET
48 Pins
DD
via a
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