UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 470

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.2 Addresses
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
data matches the data values stored in the slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
15.5.3 Transfer direction specification are written to the IICA shift register (IICA). The received addresses are
written to IICA.
15.5.3 Transfer direction specification
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
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The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
The slave address is assigned to the higher 7 bits of IICA.
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device
operation.
operation.
INTIICA0
INTIICA0
SDAA0
SDAA0
SCLA0
SCLA0
Figure 15-18. Transfer Direction Specification
A6
A6
CHAPTER 15 SERIAL INTERFACE IICA
1
1
Preliminary User’s Manual U19111EJ2V1UD
A5
A5
2
2
Figure 15-17. Address
A4
A4
3
3
Address
A3
A3
4
4
A2
A2
5
5
A1
A1
Transfer direction specification
6
6
A0
A0
7
7
R/W
R/W
8
8
9
9
Note
Note