UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 650

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Address: 0083H/1083H
Address: 0084H/1084H
Note Set a value that is the same as that of 0083H to 1083H because 0083H and 1083H are switched during the
Cautions 1. Be sure to clear bits 7 to 5 to “0” and set bits 3 and 2 to “1”.
Note Set a value that is the same as that of 0084H to 1084H because 0084H and 1084H are switched during the
Caution Be sure to clear bits 7 to 2 to “0”.
Remark For the on-chip debug security ID, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION.
boot swap operation.
boot swap operation.
2. The setting of OCDPSEL bit is valid while OCDONB = 1.
OCDPSEL
OCDONB
OCDEN1
OCDCK
STOP
7
0
0
1
0
1
0
1
7
0
0
0
1
1
Note
Note
Internal high-speed oscillator operation continues (However, Internal high-speed oscillation clock is
not supplied to CPU and peripheral hardware.).
Internal high-speed oscillator operation stops.
TOOLC1/P31, TOOLD1/P32
TOOLC0/X1, TOOLD0/X2
Not shifting to on-chip debug mode after reset release
Shifting to on-chip debug mode after reset release
OCDEN0
6
0
6
0
0
1
0
1
Internal high-speed oscillator operation control after execution of the STOP instruction
Figure 24-1. Format of Option Byte (3/3)
Operation disabled
Setting prohibited
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 24 OPTION BYTE
5
0
5
0
Pin selection used during on-chip debugging
OCDCK
STOP
Transition of on-chip debug mode
4
4
0
in on-chip debug mode
On-chip debug operation control
3
1
3
0
2
1
2
0
OCDPSEL
OCDEN1
1
1
OCDONB
OCDEN0
0
0