UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 618

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) When LVI is OFF upon power application (option byte: LVISTART = 0)
618
V
V
POR
PDR
(when X1 oscillation
oscillation clock (f
Internal high-speed
Internal reset signal
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
Remark V
system clock (f
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
1.8 V
CPU
2.
3.
4.
5.
6.
(V
XH
V
IH
Note 1
Note 6
Note 6
0 V
Operation
LOW-VOLTAGE DETECTOR).
V
V
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
LVI
DD
)
)
The operation guaranteed range is 1.8 V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.),
input a low level to the RESET pin before the voltage reaches to 1.8 V.
The internal voltage stabilization wait time includes the oscillation accuracy stabilization time of the
internal high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
This is a preliminary value and subject to change.
LVI
POR
PDR
)
stops
:
: POC power supply rise detection voltage
: POC power supply fall detection voltage
LVI detection voltage
Wait for oscillation
accuracy stabilization
Wait for voltage
0.5 V/ms (MIN.)
specified by software
Starting oscillation is
stabilization
Reset processing
Note 2
used for reset
Set LVI to be
Note 3
oscillation clock)
(internal high-speed
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Normal operation
Preliminary User’s Manual U19111EJ2V1UD
and Low-Voltage Detector (1/2)
Note 5
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Reset processing
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
V
specified by software
Starting oscillation is
DD
Note 4
5.5 V. To make the state at lower than 1.8 V reset
Note 5
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Wait for voltage
stabilization
specified by software
Starting oscillation is
Reset processing
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 5
Operation stops