UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 178

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
178
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Kx2-L microcontrollers.
Therefore, the relationship between the CPU clock (f
in Table 5-2.
Address: FFFBH
Symbol
PCC
Notes 1. Bit 5 is read-only.
Cautions 1. Be sure to clear bits 3 and 7 to “0”.
Remark
CLS
CSS
7
0
0
1
0
1
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock
After reset: 01H
Figure 5-6. Format of Processor Clock Control Register (PCC)
2. The peripheral hardware clock (f
operation mode select register (OSCCTL)). Refer to (3) Setting of operation mode for
subsystem clock pin.
f
f
XP
SUB
XTSTART
:
Main system clock
Subsystem clock
PCC is set.
: Subsystem clock oscillation frequency
PCC2
Other than above
Main system clock oscillation frequency
6
0
0
0
0
1
0
0
0
0
1
Note 2
Preliminary User’s Manual U19111EJ2V1UD
R/W
CHAPTER 5 CLOCK GENERATOR
PCC1
CLS
Note 1
<5>
0
0
1
1
0
0
0
1
1
0
(78K0/KC2-L)
PCC0
CSS
<4>
CPU
0
1
0
1
0
0
1
0
1
0
) and the minimum instruction execution time is as shown
CPU clock status
PRS
f
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
SUB
/2 (default)
/2
/2
/2
) is not divided when the division ratio of the
/2
2
3
4
3
0
CPU clock (f
PCC2
2
CPU
) selection
PCC1
1
PCC0
0

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