UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 463

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) IICA control register 1 (IICACTL1)
Address: FFA8H
IICACTL1
Symbol
This register is used to set the operation mode of I
IICACTL1 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits
are read-only.
Set IICACTL1, except the WUP bit, while bit 7 (IICE0) of IICA control register 0 (IICACTL0) is 0.
Reset signal generation clears this register to 00H.
Clear (0) WUP after the address has matched or an extension code has been received. The subsequent
communication can be entered by clearing (0) WUP. (The wait must be released and transmit data must be
written after WUP has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to 1.
When WUP = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master
device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a
start condition by setting (1) the STT0 bit, without waiting for the detection of the subsequent start condition or
stop condition.
Condition for clearing (WUP = 0)
Condition for clearing (CLD0 = 0)
Cleared by instruction (after address match or
extension code reception)
When the SCLA0 pin is at low level
When IICE0 = 0 (operation stop)
Reset
CLD0
WUP
WUP
7
0
1
0
1
Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (1/2)
After reset: 00H
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
The SCLA0 pin was detected at low level.
The SCLA0 pin was detected at high level.
6
0
CHAPTER 15 SERIAL INTERFACE IICA
CLD0
Preliminary User’s Manual U19111EJ2V1UD
<5>
R/W
Detection of SCLA0 pin level (valid only when IICE0 = 1)
Note 1
DAD0
<4>
2
Control of address match wakeup
C and detect the statuses of the SCLA0 and SDAA0 pins.
SMC0
<3>
Condition for setting (WUP = 1)
Condition for setting (CLD0 = 1)
Set by instruction (when MSTS0, EXC0, and COI0
are “0”, and STD0 also “0” (communication not
entered))
When the SCLA0 pin is at high level
DFC0
<2>
Note 2
1
0
0
0
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