UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 260
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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(TOE00, TOC004, TOC001)
<1> Count operation start flow
<2> Count operation stop flow
Note Care must be exercised when setting TOC00. For details, refer to 6.3 (3) 16-bit timer output control
Compare match interrupt
Compare match interrupt
Timer output control bits
(TMC003, TMC002)
TMC003, TMC002 bits = 0, 1
TMC003, TMC002 bits = 0, 0
register 00 (TOC00).
Compare register
Compare register
CR000/CR010 register,
Register initial setting
TMC00.TMC001 bit,
TM00 register
TOC00 register
Operable bits
TO00 output
PRM00 register,
CRC00 register,
(INTTM000)
(INTTM010)
port setting
Figure 6-39. Example of Software Processing in Free-Running Timer Mode
(CR000)
(CR010)
START
STOP
FFFFH
0000H
Note
00
,
<1>
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
N
Preliminary User’s Manual U19111EJ2V1UD
Initial setting of these registers is performed
before setting the TMC003 and TMC002
bits to 01.
Starts count operation
The counter is initialized and counting is stopped
by clearing the TMC003 and TMC002 bits to 00.
M
N
M
N
01
M
N
M
N
<2>
00
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