UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 379

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
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20 000
<R>
(5) Analog input channel specification register (ADS)
Note Setting permitted in products with operational amplifier
Cautions 1. Be sure to clear bits 4, 5, and 7 to “0”.
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Remark A/D converter analog input pins differ depending on products.
Symbol
Address: FF0EH
ADS
2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 1,
3. Set ADS after PGA operation setting when selecting the PGA output signal as analog input
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the
78K0/KY2-L:
78K0/KA2-L:
78K0/KB2-L:
78K0/KC2-L:
2 (PM1, PM2).
(refer to CHAPTER 13 OPERATIONAL AMPLIFIERS).
peripheral hardware clock (f
FOR WAIT.
Figure 12-8. Format of Analog Input Channel Specification Register (ADS)
ADOAS0
7
0
0
0
0
0
0
0
0
0
0
0
0
1
After reset: 00H
ADOAS
ANI0 to ANI3
ANI0 to ANI5
ANI0 to ANI3, ANI8 to ANI10
ANI0 to ANI10
ADS3
6
0
0
0
0
0
0
0
0
1
1
1
Other than above
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 12 A/D CONVERTER
ADS2
0
0
0
0
1
1
1
1
0
0
0
5
0
R/W
PRS
) is stopped. For details, refer to CHAPTER 31 CAUTIONS
ADS1
0
0
1
1
0
0
1
1
0
0
1
4
0
ADS0
ADS3
0
1
0
1
0
1
0
1
0
1
0
3
Analog input
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
PGAIN
Setting prohibited
channel
ADS2
2
Note
P20/ANI0 pin
P21/ANI1 pin
P22/ANI2 pin
P23/ANI3 pin
P24/ANI4 pin
P25/ANI5 pin
P26/ANI6 pin
P27/ANI7 pin
P10/ANI8 pin
P11/ANI9 pin
P12/ANI10 pin
PGA output signal
ADS1
1
Input source
ADS0
0
Note
379

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