UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 648

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

648
Address: 0080H/1080H
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
Remarks 1.
boot swap operation.
2.
2. The watchdog timer continues its operation during self-programming and EEPROM
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
4. Be sure to clear bit 7 to 0.
WINDOW1
LSROSC
WDTON
WDCS2
prohibited.
emulation of the flash memory.
delayed. Set the overflow time and window size taking this delay into consideration.
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
f
( ): f
IL
7
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
1
: Internal low-speed oscillation clock frequency
IL
Note
= 33 kHz (MAX.)
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
WINDOW0
WINDOW1
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
Figure 24-1. Format of Option Byte (1/3)
25%
50%
75%
100%
WINDOW0
Operation control of watchdog timer counter/illegal access detection
Preliminary User’s Manual U19111EJ2V1UD
WDCS0
CHAPTER 24 OPTION BYTE
5
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
7
8
9
10
12
14
15
17
Internal low-speed oscillator operation
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
During processing, the interrupt acknowledge time is
(3.88 ms)
(7.76 ms)
(15.52 ms)
4
(31.03 ms)
(124.12 ms)
(496.48 ms)
(992.97 ms)
(3.97 s)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
WDCS1
2
WDCS0
1
LSROSC
0