UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 460

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

460
Remark
Note If the wait state is canceled by setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) to 1
Condition for clearing (EXC0 = 0)
Condition for clearing (COI0 = 0)
Condition for clearing (TRC0 = 0)
<Both master and slave>
<Master>
<Slave>
<When not used for communication>
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Cleared by WREL0 = 1
When ALD0 changes from 0 to 1 (arbitration loss)
Reset
When “1” is output to the first byte’s LSB (transfer
direction specification bit)
When a start condition is detected
When “0” is input to the first byte’s LSB (transfer
direction specification bit)
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
When a start condition is detected
When a stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 changes from 1 to 0 (operation stop)
Reset
EXC0
TRC0
COI0
0
1
0
1
0
1
at the ninth clock when bit 3 (TRC0) of the IICA status register 0 (IICAS0) is 1, TRC0 is cleared,
and the SDAA0 line goes into a high-impedance state.
LREL0:
IICE0:
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (2/3)
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDAA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDAA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Extension code was not received.
Extension code was received.
Bit 6 of IICA control register 0 (IICACTL0)
Bit 7 of IICA control register 0 (IICACTL0)
Note
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
(wait cancel)
Detection of extension code reception
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (EXC0 = 1)
Condition for setting (COI0 = 1)
Condition for setting (TRC0 = 1)
<Master>
<Slave>
When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
When the received address matches the local
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
When a start condition is generated
When “0” is output to the first byte’s LSB (transfer
direction specification bit)
When “1” is input to the first byte’s LSB (transfer
direction specification bit)