UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 205

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
Caution
(3) CPU operating with subsystem clock (D) after reset release (A)
(A)
Status Transition
(A)
(A)
Status Transition
(A)
(A)
Table 5-6 shows transition of the CPU clock and examples of setting the SFR registers.
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figure 5-18 and 5-19.
(The CPU operates with the internal high-speed oscillation clock (B) immediately after a reset release.)
(The CPU operates with the internal high-speed oscillation clock (B) immediately after a reset release.)
Note 78K0/KC2-L only
(B)
(B)
(B)
(B)
(B)
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer
to CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET VALUES)).
(C) (X1 clock)
(C) (external main system clock)
(D) (XT1 clock)
(D) (external subsystem clock)
2. EXCLK, OSCSEL, EXCLKS, OSCSELS:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
:
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (1/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Bits 7 to 4 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
SFR registers do not have to be set (default status after reset release).
EXCLK
XTSTART
0
1
0
1
0
OSCSEL
1
1
EXCLKS
1
0
Note
SFR Register Setting
MSTOP
0
0
OSCSELS
1
1
Must not be
Register
checked
Must be
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
CSS
MCM0
1
1
1
1
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