UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 453

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) SO latch
(4) Wakeup controller
(5) Serial clock counter
(6) Interrupt request signal generator
(7) Serial clock controller
(8) Serial clock wait controller
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
(10) Data hold time correction circuit
(11) Start condition generator
(12) Stop condition generator
Note Bit 0 is fixed to 0.
The SO latch is used to retain the SDAA0 pin’s output level.
This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the
address value set to the slave address register 0 (SVA0) or when an extension code is received.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
This circuit controls the generation of interrupt request signals (INTIICA0).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark
In master mode, this circuit generates the clock output via the SCLA0 pin from a sampling clock.
This circuit controls the wait timing.
These circuits generate and detect each status.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
This circuit generates a stop condition when the SPT0 bit is set to 1.
2
C interrupt request is generated by the following two triggers.
Address: FFA6H
Symbol
SVA0
WTIM0 bit: Bit 3 of IICA control register 0 (IICACTL0)
SPIE0 bit: Bit 4 of IICA control register 0 (IICACTL0)
Figure 15-4. Format of Slave Address Register 0 (SVA0)
7
After reset: 00H
CHAPTER 15 SERIAL INTERFACE IICA
6
Preliminary User’s Manual U19111EJ2V1UD
5
R/W
4
3
2
1
0
Note
0
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