UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 477

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.9 Address match detection method
address.
address has been set to the slave address register 0 (SVA0) and when the address set to SVA0 matches the slave
address sent by the master device, or when an extension code has been received.
15.5.10 Error detection
register (IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted
IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
15.5.11 Extension code
In I
Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when a local
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(2) If “11110
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
C bus mode, the status of the serial data bus (SDAA0) during data transmission is captured by the IICA shift
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIICA0) is issued at the falling edge
of the eighth clock. The local address stored in the slave address register 0 (SVA0) is not affected.
the results are as follows. Note that INTIICA0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IICA control register 0 (IICACTL0) to 1 to set the standby mode for the next
communication operation.
Remark
Slave Address
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
EXC0: Bit 5 of IICA status register 0 (IICAS0)
COI0: Bit 4 of IICA status register 0 (IICAS0)
For extension codes other than the above, refer to THE I
0” is set to SVA0 by a 10-bit address transfer and “11110
Table 15-3. Bit Definitions of Main Extension Code
R/W Bit
CHAPTER 15 SERIAL INTERFACE IICA
0
0
1
COI0 = 1
Preliminary User’s Manual U19111EJ2V1UD
General call address
10-bit slave address specification (for address authentication)
10-bit slave address specification (for read command issuance
after address match)
Description
2
C-BUS SPECIFICATION published by NXP.
0” is transferred from the master device,
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