UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 670

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

670
16-bit data
transfer
8-bit
operation
Instruction
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Notes 1.
Group
2.
3.
4.
MOVW
XCHW
ADD
ADDC
Mnemonic
2. This clock cycle applies to the internal ROM program.
Only when rp = BC, DE or HL
Except “r = A”
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 27 INSTRUCTION SET
Note 3
Note 3
Note 3
Note 4
Note 4
Bytes
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
6
6
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
10
10
12
12
8
8
8
8
8
5
9
5
9
9
9
8
5
9
5
9
9
9
rp
(saddrp)
sfrp
AX
(saddrp)
AX
sfrp
AX
rp
AX
(addr16)
AX
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
word
AX
(saddrp)
sfrp
rp
(addr16)
rp
word
AX
r + A
r + A + CY
A + byte
A + r
A + (saddr)
A + (addr16)
A + (HL)
A + (HL + byte)
A + (HL + B)
A + (HL + C)
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + C
A + (HL) + CY
A + (HL + byte) + CY
A + (HL + B) + CY
A + (HL + C) + CY
word
AX
AX
CPU
(saddr) + byte
(saddr) + byte + CY
) selected by the processor clock
Operation
Z AC CY
Flag