UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 528

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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(2) Serial I/O shift register 1n (SIO1n)
16.3 Registers Controlling Serial Interfaces CSI10 and CSI11
(1) Serial operation mode register 1n (CSIM1n)
528
Serial interfaces CSI10 and CSI11 are controlled by the following five registers.
Remarks 1. 78K0/KB2-L: n = 0
Remark 78K0/KB2-L:
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n)
is 0.
During reception, the data is read from the serial input pin (SI1n) to SIO1n.
Reset signal generation clears this register to 00H.
Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication).
CSIM1n is used to select the operation mode and enable or disable operation.
CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Serial operation mode register 1n (CSIM1n)
Serial clock selection register 1n (CSIC1n)
Port alternate switch control register (MUXSEL)
Port mode register x (PMx)
Port register x (Px)
2. The SSI11 pin is available only in 48-pin products of 78K0/KC2-L.
78K0/KC2-L: n = 0, 1, x = 1, 4, 6, 12
2. In the slave mode, reception is started when data is read from SIO11 with a low level input
78K0/KC2-L: n = 0, 1
to the SSI11 pin. For details on the reception operation, refer to 16.4.2 (2) Communication
operation.
n = 0, x = 1
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Preliminary User’s Manual U19111EJ2V1UD

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