UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 599

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
The operating statuses in the STOP mode are shown below.
Note
Caution The above-mentioned reset processing time will be stated after the device has been
Subsystem clock
(XT1 oscillation)
Status of CPU
Reset signal
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
78K0/KC2-L only
Maskable interrupt
request
Reset
: don’t care
evaluated.
Table 19-2. Operation in Response to Interrupt Request in HALT Mode
Release Source
(subsystem clock)
Normal operation
(3) When subsystem clock is used as CPU clock
Figure 19-4. HALT Mode Release by Reset (2/2)
CHAPTER 19 STANDBY FUNCTION
Preliminary User’s Manual U19111EJ2V1UD
instruction
Oscillates
HALT
MK
0
0
0
0
0
1
HALT mode
PR
0
0
1
1
1
IE
0
1
0
1
Oscillation
stopped
period
Reset
ISP
Starting XT1 oscillation is
1
0
1
processing
(TBD)
Oscillation
specified by software.
Reset
stopped
Next address
instruction execution
Interrupt servicing
execution
Next address
instruction execution
Interrupt servicing
execution
HALT mode held
Reset processing
Normal operation mode
(internal high-speed
Note
oscillation clock)
Operation
Oscillates
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