UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 465

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(5) IICA low-level width setting register (IICWL)
(6) IICA high-level width setting register (IICWH)
(7) Port input mode register 6 (PIM6)
This register sets the input buffer of P60 or P61 in 1-bit units. When using an input compliant with the SMBus
specifications in I
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FF3EH
This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA
being in master mode.
IICWL can be set by an 8-bit memory manipulation instruction.
Set IICWL when bit 7 (IICE0) of IICA control register 0 (IICACTL0) is 0.
Reset signal generation sets this register to FFH.
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA
being in master mode.
IICWH can be set by an 8-bit memory manipulation instruction.
Set IICWH when bit 7 (IICE0) of IICA control register 0 (IICACTL0) is 0.
Reset signal generation sets this register to FFH.
Symbol
PIM6
PIM6n
Figure 15-10. Format of IICA High-Level Width Setting Register (IICWH)
2
Figure 15-9. Format of IICA Low-Level Width Setting Register (IICWL)
C communication, select the SMBus input buffer.
7
0
0
1
Address: FFADH
Address: FFAEH
After reset: 00H
Symbol
Symbol
IICWH
IICWL
Figure 15-11. Format of Port Input Mode Register 6 (PIM6)
Normal input (Schmitt) buffer
SMBus input buffer
6
0
7
7
CHAPTER 15 SERIAL INTERFACE IICA
R/W
Preliminary User’s Manual U19111EJ2V1UD
After reset: FFH R/W
After reset: FFH R/W
6
6
5
0
5
5
P6n pin input buffer selection (n = 0, 1)
4
0
4
4
3
3
3
0
2
2
2
0
1
1
0
0
PIM61
1
PIM60
0
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