UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 458

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

458
Caution When bit 3 (TRC0) of the IICA status register 0 (IICAS0) is set to 1, WREL0 is set to 1
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition
Cautions concerning set timing
Condition for clearing (SPT0 = 0)
Remark
For master reception:
For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Cannot be set to 1 at the same time as STT0.
SPT0 can be set to 1 only when in master mode
When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks,
note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be
changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during
the wait period that follows the output of the ninth clock.
Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Cleared by loss in arbitration
Automatically cleared after stop condition is detected
Cleared by LREL0 = 1 (exit from communications)
When IICE0 = 0 (operation stop)
Reset
SPT0
0
1
generated before the first stop condition is detected following the switch to the operation enabled
status.
during the ninth clock and wait is canceled, after which TRC0 is cleared and the SDAA0
line is set to high impedance.
Bit 0 (SPT0) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDAA0 line goes to low level, either set the SCLA0 line to high level or wait until it goes to high
level. Next, after the rated amount of time has elapsed, the SDAA0 line changes from low level to high
level and a stop condition is generated.
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave
has been notified of final reception.
Therefore, set it during the wait period that follows output of the ninth clock.
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
Note
.
Stop condition trigger
Condition for setting (SPT0 = 1)
Set by instruction