UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 614

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
Remark
614
Reset function
Low-voltage detector
Interrupt
Regulator
2.
The special function registers (SFRs) mounted depend on the product. Refer to 3.2.3 Special function
registers (SFRs).
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Table 20-2. Hardware Statuses After Reset Acknowledgment (4/4)
Reset Source
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable registers 0, 1 (EGPCTL0, EGPCTL1)
External interrupt falling edge enable registers 0, 1 (EGNCTL0, EGNCTL1)
Regulator mode control register (RMC)
WDTRF flag
LVIRF flag
Cleared (0)
Cleared (00H)
0FH
RESET Input
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 20 RESET FUNCTION
Hardware
Cleared (0)
Cleared (00H)
0FH
Reset by POC
Set (1)
Held
Cleared (00H)
0FH
Reset by WDT
Held
Set (1)
Held
Reset by LVI
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
Acknowledgment
Status After Reset
Note 2
Note 2
Note 2
Note 1