UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 591

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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19.1 Standby Function and Configuration
19.1.1 Standby function
available.
(1) HALT mode
(2) STOP mode
set are held. The I/O port output latches and output buffer statuses are also held.
The standby function is mounted onto all 78K0/Kx2-L microcontroller products.
The standby function is designed to reduce the operating current of the system. The following two modes are
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem
clock oscillator
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
Note 78K0/KC2-L only
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
3. The following sequence is recommended for operating current reduction of the A/D converter
4. Stop the operational amplifier before executing the STOP instruction.
subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU
is operating on either the main system clock or the subsystem clock.
operating with main system clock before executing STOP instruction.
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then
execute the STOP instruction.
Note
is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
CHAPTER 19 STANDBY FUNCTION
Preliminary User’s Manual U19111EJ2V1UD
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