UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 424
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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424
Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The
Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during
7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
8. When the TXDLV6 bit is set to 1 (inverted TxD6 output), the TxD6/SCLA0/P60 pin (78K0/KY2-
TXDLV6
SBL62
DIR6
L, 78K0/KA2-L) or TxD6/P13 pin (78K0/KB2-L, 78K0/KC2-L) cannot be used as a general-
purpose port, regardless of the settings of POWER6 and TXE6.
TxD6/SCLA0/P60 or TxD6/P13 pin as a general-purpose port, clear the TXDLV6 bit to 0
(normal TxD6 output).
status of the SBRF6 flag is held (1).
After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before
an interrupt request signal is generated).
reception has been correctly completed.
1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed
(before an interrupt request signal is generated).
SBF transmission.
transmission.
1
1
1
0
0
0
0
1
0
1
0
1
MSB
LSB
Normal output of T
Inverted output of T
SBL61
0
1
1
0
0
1
1
0
CHAPTER 14 SERIAL INTERFACE UART6
Preliminary User’s Manual U19111EJ2V1UD
SBL60
X
X
D6
1
0
1
0
1
0
1
0
D6
SBF is output with 13-bit length.
SBF is output with 14-bit length.
SBF is output with 15-bit length.
SBF is output with 16-bit length.
SBF is output with 17-bit length.
SBF is output with 18-bit length.
SBF is output with 19-bit length.
SBF is output with 20-bit length.
Enables/disables inverting T
First-bit specification
SBF transmission output width control
X
D6 output
When using the
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