UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 587

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
17.4.4 Interrupt request hold
executed, request acknowledgment is held pending until the end of execution of the next instruction.
instructions (interrupt request hold instructions) are listed below.
CPU processing
There are instructions where, even if an interrupt request is issued for them while another instruction is being
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
Figure 17-23 shows the timing at which interrupt requests are held pending.
Remarks 1. Instruction N: Interrupt request hold instruction
MOV PSW, #byte
MOV A, PSW
MOV PSW, A
MOV1 PSW. bit, CY
MOV1 CY, PSW. bit
AND1 CY, PSW. bit
OR1 CY, PSW. bit
XOR1 CY, PSW. bit
SET1 PSW. bit
CLR1 PSW. bit
RETB
RETI
PUSH PSW
POP PSW
BT PSW. bit, $addr16
BF PSW. bit, $addr16
BTCLR PSW. bit, $addr16
EI
DI
Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and
PR1H registers.
the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged.
2. Instruction M: Instruction other than interrupt request hold instruction
3. The
IF
PR (priority level) values do not affect the operation of
Instruction N
Figure 17-23. Interrupt Request Hold
CHAPTER 17 INTERRUPT FUNCTIONS
Preliminary User’s Manual U19111EJ2V1UD
Instruction M
PSW and PC saved, jump
to interrupt servicing
IF (interrupt request).
Interrupt servicing
program
These
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