UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 403

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
<R>
(3) Port mode registers 1 and 2 (PM1, PM2)
Cautions 1. Set the pin set to analog input to the input mode by using port mode register 1 (PM1).
When using AMP0-/ANI0/P20, AMP0OUT/PGAIN/ANI1/P21, and AMP0+/ANI2/P22 pins for the operational
amplifier 0, set PM20 to PM22 to 1.
When using AMP1-/ANI8/P10, AMP1OUT/ANI9/P11, and AMP1+/ANI10/P12 pins for the operational amplifier 1,
set PM10 to PM12 to 1.
The output latches of P20 to P22 and P10 to P12 at this time may be 0 or 1.
If PM20 to PM22 and PM10 to PM12 are set to 0, they cannot be used as the operational amplifier 0 and 1 pins.
PM1 and PM2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Address: FF2FH
Symbol
ADPC1
Symbol
Address: FF21H
PM1
2. If data is written to ADPC1, a wait cycle is generated. Do not write data to ADPC1 when the
Remark The figure shown above presents the format of port mode register 1 of the 78K0/KB2-L and
peripheral hardware clock is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.
ADPCSn
PM17
PM1n
7
0
0
1
7
Figure 13-5. Format of A/D Port Configuration Register 1 (ADPC1)
After reset: 07H
0
1
78K0/KC2-L.
After reset: FFH
Analog input
Digital I/O
Output mode (output buffer on)
Input mode (output buffer off)
Figure 13-6. Format of Port Mode Register 1 (PM1)
PM16
6
0
6
CHAPTER 13 OPERATIONAL AMPLIFIERS
(78K0/KB2-L and 78K0/KC2-L Only)
R/W
Preliminary User’s Manual U19111EJ2V1UD
PM15
5
5
0
R/W
Digital I/O or analog input selection (n = 8 to 10)
P1n pin I/O mode selection (n = 0 to 7)
PM14
4
4
0
PM13
3
3
0
PM12
ADPCS10
2
2
PM11
1
ADPCS9
1
PM10
0
ADPCS8
0
403

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