UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 479

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCLA0 is at low level while attempting to generate a
restart condition
Notes 1. When WTIM0 (bit 3 of IICA control register 0 (IICACTL0)) = 1, an interrupt request occurs at the falling
Remark
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
edge of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an
interrupt request occurs at the falling edge of the eighth clock.
SPIE0: Bit 4 of IICA control register 0 (IICACTL0)
Table 15-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
Note 2
Note 2
Note 1
Note 1
Note 1
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