UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 153

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Pull-up resistor option registers (PUxx)
Symbol
P12
P0
P1
P2
P3
P4
P6
P7
These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can
be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor
has been specified in these registers. On-chip pull-up resistors cannot be connected to bits set to output mode
and bits used as alternate-function output pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H (sets only PU12 to 20H).
P27
Notes 1. 48-pin products only
Pmn
P17
7
0
0
0
0
0
0
0
1
Note 2
2. If this pin is set as an analog input and to input mode, do not access the output latch.
3. “0” is always read from the output latch of the pin in the X1 oscillation mode, XT1 oscillation
4. P121 to P125 are read-only.
P26
Output 0
Output 1
P16
mode, or external clock input mode.
6
0
0
0
0
0
0
Note 2
Output data control (in output mode)
P25
P75
P125
P15
5
0
0
0
0
Note 2
Note 1
Figure 4-37. Format of Port Register (78K0/KC2-L)
P124
P24
P74
P14
4
0
0
0
0
Note 2
Note 1
Preliminary User’s Manual U19111EJ2V1UD
Note 3
CHAPTER 4 PORT FUNCTIONS
P123
P23
P13
P33
P63
P73
3
0
0
Note 2
Note 3
m = 0 to 4, 6, 7, 12 to 14; n = 0 to 7
P122
P02
P12
P22
P42
P32
P62
P72
2
Note 1
Note 2
Note 2
Note 1
Note 3
P121
P11
P21
P01
P31
P41
P61
P71
1
Note 2
Note 2
Note 3
Input low level
Input high level
P10
P20
P120
P00
P30
P40
P60
P70
0
Note 2
Note 2
Input data read (in input mode)
Address
FF0CH
FF00H
FF01H
FF02H
FF03H
FF04H
FF06H
FF07H
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch)
00H (output latch) R/W
After reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
153
Note 4