UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 475

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.7 Canceling wait
resumed.
register 0 (IICACTL0) to 1.
output to SDAA0 because the timing for changing the SDAA0 line conflicts with the timing for writing IICA.
so that the wait state can be canceled.
IICACTL0, so that the wait state can be canceled.
The I
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of IICA control
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICACTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICACTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL0 to 1, an incorrect value may be
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
If the I
Caution If a processing to cancel a wait state executed when WUP (bit 7 of IICA control register 1
Writing data to IICA shift register (IICA)
Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait)
Setting bit 1 (STT0) of IICACTL0 register (generating start condition)
Setting bit 0 (SPT0) of IICACTL0 register (generating stop condition)
Note Master only
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
(IICACTL1)) = 1, the wait state will not be canceled.
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
2
C cancels the wait state and communication is
Note
Note
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