UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 218

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

218
Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI000 pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
(i) When CR010 is used as a compare register
(ii) When CR010 is used as a capture register
(iii) Setting range when CR000 or CR010 is used as a compare register
The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal
(INTTM010) is generated if they match.
Caution CR010 does not perform the capture operation when it is set in the comparison mode, even
The count value of TM00 is captured to CR010 when a capture trigger is input.
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 pin valid edge is set
by PRM00.
When CR000 or CR010 is used as a compare register, set it as shown below.
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM00 register) is changed from 0000H to 0001H.
Address: FF14H, FF15H
When the timer counter is cleared due to overflow
When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by
TI000 pin valid edge input)
When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM00 and CR000 (CR000 = other than 0000H, CR010 = 0000H))
CR010
Operation
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
if a capture trigger is input to it.
15
14
13
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
12
After reset: 0000H
FF15H
Preliminary User’s Manual U19111EJ2V1UD
11
0000H < N
0000H
M < N
0000H
CR000 Register Setting Range
10
Note
Note
FFFFH
N
N
9
FFFFH
FFFFH
FFFFH (N
R/W
8
7
M)
6
5
0000H
Normally, this setting is not used. Mask the
match interrupt signal (INTTM010).
0000H
0000H
0000H
FF14H
4
Note
Note
Note
Note
CR010 Register Setting Range
3
M
M
M < N
M
2
FFFFH
FFFFH
FFFFH (M
1
0
N)