UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 469

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5 I
Figure 15-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
low level period can be extended and a wait can be inserted.
15.5.1 Start conditions
level. The start conditions for the SCLA0 pin and SDAA0 pin are signals that the master device generates to the slave
device when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
has been detected (SPD0: Bit 0 of the IICA status register 0 (IICAS0) = 1). When a start condition is detected, bit 1
(STD0) of IICAS0 is set (1).
2
C bus’s serial data bus.
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCLA0) is continuously output by the master device. However, in the slave device, the SCLA0’s
A start condition is met when the SCLA0 pin is at high level and the SDAA0 pin changes from high level to low
A start condition is output when bit 1 (STT0) of IICA control register 0 (IICACTL0) is set (1) after a stop condition
2
C Bus Definitions and Control Methods
SDAA0
SCLA0
Start
condition
Figure 15-15. I
Address R/W ACK
1-7
SDAA0
SCLA0
CHAPTER 15 SERIAL INTERFACE IICA
2
C bus’s serial data communication format and the signals used by the I
Preliminary User’s Manual U19111EJ2V1UD
Figure 15-16. Start Conditions
8
H
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
Data
1-8
ACK
9
Stop
condition
2
C bus.
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