UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 125
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(1) Oscillator
(2) IDLE control
(3) HALT control
(4) PLL
(5) Prescaler 1
(6) Prescaler 2
(7) Oscillation stabilization time wait control (OST)
(8) Clock monitor
Note The CLMER signal (low level) is valid only when P16 is specified as an output port or the TOQ00 output
The main resonator oscillates the following frequencies (f
• In PLL mode (×8 fixed): f
• In clock-through mode: f
All functions other than the oscillator, PLL, clock monitor operation, and CSIB in slave mode are stopped.
Only the CPU clock (f
This circuit multiplies the clock generated by the oscillator (f
It operates in two modes: clock-through mode in which f
control register (PLLCTL), and PLL mode in which a multiplied clock is output.
The output frequency of PLL is 20 MHz in the PLL mode.
This prescaler generates the clock (f
This circuit divides the system clock (f
The clock (f
This unit measures the time from when the clock generated by the oscillator was input until oscillation is
stabilized. It also counts the PLL lockup time. The count clock can be selected from 2
The clock monitor samples the clock generated by the oscillator (f
When it detects an error (stop of oscillation), the output of the motor control timer goes into a high-impedance
state. The CLMER signal (low level)
and CHAPTER 9 MOTOR CONTROL FUNCTION). Low-level output is released by reset signal.
function.
XX
to f
XX
/8) to be supplied to the CPU clock (f
CPU
) is stopped.
X
X
= 2.5 MHz (f
= 2.5 MHz (f
CHAPTER 5 CLOCK GENERATOR
XX
Note
XX
User’s Manual U17716EJ2V0UD
to f
).
is output from P16 (for details, see CHAPTER 4 PORT FUNCTIONS
XX
XX
XX
= 2.5 MHz)
= 20 MHz)
/2,048) to be supplied to on-chip peripheral functions.
CPU
X
X
):
is output as is by setting the SELPLL bit of the PLL
) and internal system clock (f
X
) by 8.
X
), by using the internal oscillation clock.
14
/f
CLK
X
to 2
) is generated.
16
/f
X
.
123
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