UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 230

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
228
Note The TPkOVF0 and TPkOVF1 flags are set on the internal RAM by software.
<1> Read the TPkCCR0 register (setting of the default value of the TIPk0 pin input).
<2> Read the TPkCCR1 register (setting of the default value of the TIPk1 pin input).
<3> An overflow occurs. Nothing is done by software.
<4> Read the TPkCCR0 register.
<5> Read the TPkCCR1 register.
<6> Same as <3>
Remark
TPkCCR0 register
TPkCCR1 register
Example when two capture registers are used (without using overflow interrupt)
INTTPkOV signal
TPkOVF0 flag
TPkOVF1 flag
Read the overflow flag. If the overflow flag is 1, set only the TPkOVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read.
Read the TPkOVF1 flag. If the TPkOVF1 flag is 1, clear it to 0.
Because the TPkOVF1 flag is 1, the pulse width can be calculated by (10000H + D
(correct).
TIPk0 pin input
TIPk1 pin input
16-bit counter
TPkOVF bit
k = 0, 2
TPkCE bit
FFFFH
0000H
Note
Note
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D
00
User’s Manual U17716EJ2V0UD
<1>
D
10
<2>
D
00
<3>
D
D
01
10
<4>
D
11
<5> <6>
D
01
D
11
01
− D
00
).
11
− D
10
(2/2)
)

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