UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 209
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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PWM waveform from the TOPm1 pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTPmCC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
When the TPmCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TPmCCRa register while the counter is operating. The newly
The compare match interrupt request signal INTTPmCC0 is generated when the 16-bit counter counts next time
The value set to the TPmCCRa register is transferred to the CCRa buffer register when the count value of the 16-
Remark
Active level width = (Set value of TPmCCR1 register) × Count clock cycle
Cycle = (Set value of TPmCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TPmCCR1 register)/(Set value of TPmCCR0 register + 1)
CCR0 buffer register
CCR1 buffer register
INTTPmCC0 signal
INTTPmCC1 signal
TPmCCR0 register
TPmCCR1 register
m = 0, 2, 3, a = 0, 1
TOPm1 pin output
TOP00 pin output
16-bit counter
TPmCE bit
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-32. Basic Timing in PWM Output Mode
Active period
(D
D
10
10
D
)
User’s Manual U17716EJ2V0UD
00
D
D
(D
00
10
D
D
Cycle
D
00
10
10
D
00
+ 1)
00
D
Inactive period
(D
10
D
00
00
- D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01
207
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