UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 375

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

HZAyCTLn
After reset: 00H
n = 0, 1
y = 0, 1
HZAyDCEn
HZAyDCMn
HZAyDCEn
HZAyDCNn
HZAyDCTn
Rewrite the HZAyDCMn bit when the HZAyDCEn bit = 0.
• Rewrite the HZAyDCNn and HZAyDCPn bits when the HZAyDCEn bit is 0.
• For the edge specification of the INTP0 to INTP3 pins, see 14.4.2 (1) External
• High-impedance output control is performed when the valid edge is input after the
• If an edge indicating abnormality is input to the external pin
• The HZAyDCTn bit is always 0 when it is read because it is a software-triggered
• The HZAyDCTn bit is invalid even if it is set to 1 when the HZAyDCEn bit = 0.
• Simultaneously setting the HZAyDCTn and HZAyDCCn bits to 1 is prohibited.
interrupt rising edge specification register 0 (INTR0), external interrupt
falling edge specification register 0 (INTF0).
operation is enabled (by setting HZAyDCEn bit to 1). If the external pin
the active level when the operation is enabled, therefore, high-impedance output
control is not performed.
according to the setting of the HZAyDCNn and HZAyDCPn bits), the HZAyDCTn
bit is invalid even if it is set to 1.
bit.
<7>
Note HZA0CTL0: TOQH0OFF pin, HZA0CTL1: TOP2OFF pin,
0
1
0
1
0
0
1
1
0
1
R/W
HZAyDCMn HZAyDCNn HZAyDCPn HZAyDCTn HZAyDCCn
CHAPTER 9 MOTOR CONTROL FUNCTION
Disable high-impedance output control operation. Pins can function as
output pins.
Enable high-impedance output control operation.
Setting of the HZAyDCCn bit is valid regardless of the external pin
input.
Setting of the HZAyDCCn bit is invalid while the external pin
holds a level detected as abnormal (active level).
No operation
Pins are made to go into a high-impedance state by software and the
HZAyDCFn bit is set to 1.
HZAyDCPn
HZA1CTL0: TOQ1OFF pin, HZA1CTL1: TOP3OFF pin
<6>
0
1
0
1
Condition of clearing high-impedance state by HZAyDCCn bit
Address: HZA0CTL0 FFFFF5F0H, HZA0CTL1 FFFFF5F1H,
User’s Manual U17716EJ2V0UD
No valid edge (setting the HZAyDCFn bit by external pin
input is prohibited).
Rising edge of the external pin
(abnormality is detected by rising edge input).
Falling edge of the external pin
(abnormality is detected by falling edge input).
Setting prohibited
5
HZA1CTL0 FFFFF630H, HZA1CTL1 FFFFF631H
High-impedance output trigger bit
High-impedance output control
External pin
4
Note
<3>
input edge specification
Note
Note
input is valid
input is valid
<2>
Note
(which is detected
1
0
Note
Note
input
HZAyDCFn
Note
is at
Note
<0>
(1/2)
373